1. Field of the Invention
The present invention relates to a wiring substrate on which an electronic component is flip-chip bonded and an electronic component mounting structure.
2. Description of Related Art
There is know a semiconductor device in which a semiconductor element 102 is mounted on one surface side of a wiring substrate 100 in which wiring patterns are stacked in a multi-layered fashion, and solder balls 110, 110 as external connection terminals are mounted on the other surface side of the wiring substrate 100, as shown in FIG. 6.
In this semiconductor device, in a mounting surface of the wiring substrate 100 on which the semiconductor element 102 is mounted, tip ends of bumps formed on electrode terminals 102a, 102a of the semiconductor element 102 contact with conductive patterns 106 and then they are bonded by solder 108.
In this semiconductor device, an underfill resin 112 is filled in a clearance between a surface of the wiring substrate 100 and the semiconductor element 102.
In the semiconductor device shown in FIG. 6, the conductive patterns 106, 106 are formed on the mounting surface of the wiring substrate 100 so as to be exposed at a position where the tip ends of the bumps 104, 104 of the semiconductor device 102 as shown in FIG. 7. In the conductive pattern 106, a wide portion 106a of which width is wider than other portions is formed in a middle portion of the conductive pattern 106. The tip end of the bump 104 of the semiconductor device 102 comes into contact with the wide portion 106a. 
Both ends of the conductive pattern 106, 106 are covered with solder resists 114, 116.
When the semiconductor element 102 is flip-chip bonded on the mounting surface of the wiring substrate 100 shown in FIG. 7, Japanese Patent Unexamined Publications JP-A-11-186322 and JP-A-2000-77471 proposes following bonding methods.
That is, solder powders are applied to whole exposed surfaces of the conductive patterns 106, 106, then the solder powders are fused to cover the wide portion 106a of the conductive pattern 106 with fused solder, and then the tip end of the bump 104 of the semiconductor element 102 is brought into contact with the wide portions 106a of the conductive patterns 106. At this time, the solder 108 covering whole exposed surfaces of the conductive patterns 106 gathers around peripheral surfaces of the bumps 104 respectively due to a surface tension, then, the gathered solder becomes solidified and joins together the bumps 104 and the conductive patterns 106.
According to the semiconductor element mounting structure proposed in JP-A-11-186322 and JP-A-2000-77471, the solder that covers whole exposed surfaces of the conductive patterns 106 can be utilized in joining the bumps 104 of the semiconductor element 102 and the conductive patterns 106. Thus, both can be connected electrically without fail.
However, the conductive patterns 106, 106 exposed on the mounting surface of the wiring substrate 100 are formed sometimes such that, as shown in FIG. 8, the interval between adjacent conductive patterns 106, 106 becomes narrow or wide depending upon the relationship to the electrode terminals 102a, 102a of the mounted semiconductor element 102.
In such situation, as shown in FIG. 8, if respective exposed lengths of the conductive patterns 106, 106 are equal mutually, when bringing the tip end of the bump 104 of the semiconductor device 102 into contact with the wide portion 106a of the conductive pattern 106 which is covered with fused solder, in a region where an interval between the adjacent conductive pattern 106 is narrow, as shown in FIG. 9, the solder 108 which is gathered around the adjacent bumps 104 approaches each other and there is a possibility of contacting each other. This causes shortcircuit between the electrode terminals 102a, 102a. 